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6 Command Interface
There are two types of bus cycles and timing sequences that occur in the PCMCIA type interface, direct mapped I/O
transfer and memory access. Two types of bus cycles are also available in True IDE interface type: PIO transfer and
Multi-Word DMA transfer.
Table 18, Table 19, Table 20, Table 21, Table 22, Table 23, Table 24, and Table 25 show the read and write timing
parameters. Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, Figure 7, and Figure 8 and Figure 9 show the read and
write timing diagrams.
In order to set the card mode, the – OE (-ATASEL) signal must be set and kept stable before applying VCC until the
reset phase is completed. To place the card in Memory mode or I/O mode, -OE (-ATASEL) must be driven High,
while it must be driven Low to place the card in True IDE mode.
6.1 Attribute Memory Read and Write
Figure 2: Attribute Memory Read waveforms
Table 18: Attribute Memory Read timing
Speed version
300ns
Item
Symbol
IEEEE Symbol
Min. (ns)
Max. (ns)
Read Cycle Time
Address Access Time
Card Enable Access Time
Output Enable Access Time
Output Disable Time from CE
Output Disable Time from OE
Output Enable Time from CE
Output Enable Time from OE
Data Valid from Address Change
Address Setup Time
tcI
ta(A)
ta(CE)
ta(OE)
tdis(CE)
tdis(OE)
ten(CE)
ten(OE)
tv(A)
tsu(A)
tAVAV
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
tELQNZ
tGLQNZ
tAXQX
tAVWL
300
5
5
0
30
300
300
150
100
100
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.20
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
C-320_data_sheet_CF-HxBO_Rev120.doc
Page 18 of 101
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